The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a high-speed peaking circuit for a semiconductor tester channel architecture.
The performance of a computer system often relies heavily on the relative speeds of the processor and the supporting memory. Conventional memory devices such as dynamic random access memory (DRAM) currently operate at around 125 MHz, while personal computer processors typically operate in the range from 250 MHz to over 1 Gigahertz. New memory technologies that improve upon conventional DRAM, such as double-data-rate DRAM, SDRAM, and Rambus DRAM promise to increase memory processing speeds up to and beyond 800 Mhz to bridge the performance gaps between memory devices and processors.
In order to test semiconductor devices that employ high-speed memory technology, or that are adapted to interface with such technology, semiconductor device manufacturers employ sophisticated automatic test equipment (ATE). The ATE must be able to generate high speed test waveforms, apply the waveforms to individual device pins, and capture the outputs from the device-under-test (DUT) for analysis to expected results.
Referring generally to FIG. 1, the ATE tester signals are usually generated by drivers 12 to propagate along carefully controlled fifty-ohm transmission lines to corresponding pins of a device-under-test (DUT) 13. To properly match the fifty-ohm transmission lines, the comparator and driver circuitry employ a fifty-ohm backmatch resistance. The output signals from the DUT propagate back to the tester along another set of transmission lines and are captured by comparators 14. The driver/comparator circuitry is often termed the xe2x80x9cpin electronicsxe2x80x9d, and mounted on channel cards. The channel cards may include, for example, up to eight channels corresponding to eight device-under-test (DUT) pins. FIG. 1 illustrates a block diagram of a generalized single channel architecture. For a 512 pin device, 64 channel cards may be employed. General background information relating to conventional testers and pin electronics may be found in U.S. Pat. Nos. 5,566,188 and 5,321,700.
Straightforward backmatching for large variations in a 50 ohm tester transmission line has commonly been employed for low-speed tester applications, such as that described in U.S. Pat. No. 5,955,890 to Gillette. The construction in Gillette utilizes a plurality of resistive switches that selectively conduct to maintain a 50 ohm transmission line environment as necessary. Unfortunately, while the Gillette scheme possibly works well for its intended low speed application, for high speed signals each unused switch would possibly create a capacitive xe2x80x9cstubxe2x80x9d, thereby further affecting the signal transmission quality.
While conventional high-performance and high-speed testers have the ability of generating high speed signals approaching 1.6 Gigahertz, the tester signal quality often experiences degradations that affect the pulse-shape as the signal propagates along the transmission line. This degradation may affect the level of the pulse by as much as ten percent. For example, FIG. 2 illustrates how minor variations in the characteristic impedance of the transmission line causes a roll-off of the leading and trailing edges of the tester signal, at 16 (leading edge shown only).
With further reference to FIG. 1, to compensate for the roll-off problem described above, conventional high speed pin electronics include xe2x80x9cpeaking circuitryxe2x80x9d 20 in the form of an RC circuit to introduce a lift in the signal at the leading and trailing edges (shown at 17, in phantom, FIG. 2). While the conventional peaking circuitry substantially improves the roll-off problem, it introduces additional resistance into the transmission line, creating a reflected bump or backmatch problem, shown in FIG. 2, at 18 (in phantom) that can affect the tester pulse level by several percent.
What is needed and heretofore unavailable is a circuit for high speed transmission line applications that cooperates with a peaking circuit to fine-tune and maximize tester signal pulse shape characteristics with minimal affect to the characteristic impedance of the tester transmission line. The peaking and backmatch circuit of the present invention satisfies this need.
The peaking and backmatch circuit of the present invention provides high accuracy semiconductor device testing for high bandwidth applications while minimizing undesirable effects on the characteristic impedance of a high speed tester channel. This correspondingly results in higher tester accuracy and performance.
To realize the foregoing advantages, the invention in one form comprises a high-speed tester channel architecture for delivering and receiving signals to and from a device-under-test. The tester channel architecture includes drive/compare circuitry having respective driver and comparator transmission line paths and backmatch circuitry to establish a backmatch condition. Peaking circuitry is disposed in each of the driver and comparator transmission line paths. The peaking circuitry includes an inductive branch and a capacitive branch disposed in each of the driver and comparator transmission line paths to preserve the backmatch condition while enhancing the tester signal pulse.
In another form, the invention comprises a method of compensating for losses to a tester signal propagating along a driver-terminated transmission line. The method includes the steps of backmatching the transmission line with a backmatch resistance and lifting the leading edge of the signal with peaking circuitry. The peaking circuitry includes inductive branch circuitry and capacitive branch circuitry to preserve the backmatching step.